
\subsection{FEC to Interleaver buffer}
\label{sec:fec_buffer}
\begin{description}
	\item[Estimated gates] 1000
	\item[Estimated data bitstream delay] None, all delay is included in the calculation for the Interleaver itself.
\end{description}

\begin{table*} \begin{tabularx}{\linewidth}{c|c|c|X}

	Name & Width & Direction & Description \\ \hline

	\wire{reset} & 1 & I & Active low reset. \\

	\wire{clk} & 1 & I & Clock. \\

	\wire{fec\_out\_bits} & 1 & I & The bitstream outputed by the
	forward error correction unit. \\

	\wire{fec\_out\_valid} & 1 & I & Indicates the bitstream
	\wire{fec\_out\_bits} is valid and should be buffered. \\


	\wire{block} & 768 & O & A block of buffered data. (768 bits = 96
	bytes). \\

	\wire{block\_valid} & 1 & O & Indicates the data block
	\wire{block} is valid and should be processed. \\

	\wire{advance} & 1 & I & Asserted by the consumer to indicate that
	the current data block has been processed completely and a new data
	block is required. \\

\end{tabularx} \caption{FEC output buffer description} 	\label{tbl:fec-buf-io} \end{table*}

\autoref{tbl:fec-buf-io} describes the inputs and outputs of this logic
block.
Transitions the data pipline from a sequence of bits to a sequence of
blocks.